DidaWiki

module rdy(rdyIn,lineaRdy,clock,betaRdyIn); 
 
 
  output rdyIn; 
  input lineaRdy, clock, betaRdyIn; 
 
  reg c; 
 
  initial
  begin
    c = 0; 
  end
 
  always @ (negedge clock) 
  begin
    if(betaRdyIn==1) 
      c = ~c; 
  end
 
  assign rdyIn = (lineaRdy == c ? 0 : 1 ) ; 
 
endmodule