DidaWiki

`timescale 1ns/1ns
 
module test_UF();
 
`define TAU 16
// `define TAU 8
 
   parameter N = 4;
 
   reg clock;
 
   reg [N-1:0] linx;
   reg [N-1:0] liny;
   reg 	       lrdy;
 
   wire        lack;
   wire [N-1:0] lor;
   wire [N-1:0] loq;
 
   UF #(N) uf1(lack, lor, loq,
	       clock,
	       lrdy, linx, liny);
 
   initial
     begin
	clock = 0;
	linx  = 9;
	liny  = 5;
	lrdy  = 0;
     end
 
   always
     begin
	#`TAU clock = 1;
	#1 clock = 0;
     end
 
   initial
     begin
	$dumpfile("test_uf.vcd");
	$dumpvars();
 
	#30
	  lrdy = 1;
 
 
	#150 $finish;
 
     end
endmodule