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====== Access to Xeon PHI ======

** This instructions are relative to the Xeon PHI Knights Corner. The additional instructions to access the PHI Knights Landing may be found [[spm1617knl|here]].**


==== Machine name  and access ====
The machine is  r720-phi.itc.unipi.it and has the IP address 131.114.137.225

In case you have not already received and account, you should request the account to the SPM teacher sending an email with 
  * SUbject: SPM PHI ACCOUNT 1718
  * Body: name, family name enrollement number and either CS or MCSN in case you are enrolled in Computer Science or in Computer Science and Networking

Once you have the account (will be an "spm16XX") you may access the host with the Xeon PHI board by 
  * ssh spm16XX@r720-phi.itc.unipi.it
You **should change the password** you received by email at first login issuing a command //passwd// at the shell prompt. 

=== Backup ===
Please take into account the homes on r720-phi.itc.unipi.it are **not** subject to backup. //Keep a local copy// of whatever (source) files you are using on the machine. In case of problems I'll not be able to recover any of the home files. 

Take into account that you may edit files on your machine and just compile and run them on the remote (host or PHI). What you can do is to have a local directory hosting the source files, may be develop and debug using local IDE (such as Eclipse or Visual Studio), then synchronize the files using the **rsync** command and execute commands on remote host via **ssh** commands from the shell prompt.

If you need further info concerning the procedure don't hesitate to ask me during question time or by email.  



=== Accessing FastFlow and sample Code/Classworks ===
The correct version of FastFlow to use for the course is actually replicated under <code>/home/spm1501/fastflow</code> and the exercises and material relative to the classworks are under <code>/home/spm1501/public</code> 
In case you want to access directly these directories under your own home directory, you may create symbolic links to the two directories by issuing commands such as: 
<code>
    link -s /home/spm1501/fastflow .
    link -s /home/spm1501/public .
</code>
that will leave two new subdirectories (link) in the current directory. 

===== Extra tools =====
All the non standard tools (or the versions newer than the ones provided in the standard distribution) are available under the directory <code>/home/spm1501/public</code>

==== Java =====
Oracle JDK 1.8 has been installed under /home/spm1501/public directory. Set up the PATH to the bin directory and please **avoid** to make local copies of it in your local home directory. Both compiler and run time have been installed. //This only works on the host//, it does not work on the Xeon PHI. 

==== Compiling and running code on the PHI ====
In order to be able to use the tools, you have to run the script in
  * **source /opt/intel/compilers_and_libraries/bin/compilervars.sh intel64** that will set up the proper compiler and library paths. I suggest you to make the execution of the script automatic by inserting the call to the script in the **.bashrc** configuration file of your home directory (add a line such as **source /opt/intel/composerxe/bin/compilervars.sh intel64** at the end of this file)

In order to run a program on PHI: 
  - compile it on the host using **icc** with the additional flag  **-mmic**
  - copy the executable to the mic0 or mic1 with a **scp a.out mic0:**
  - execute it on the mic: **ssh mic0 ./a.out**

Please take into account that a minimal set of libraries is available on the mic.  

=== FastFLow ===
There are a few things to take into account when using FastFlow on PHI: 

  * please take into account that you need to include the flag <code>-DNO_DEFAULT_MAPPING</code> when compiling FastFlow programs, as the default mapping at the moment assumes a core numbering such as the one used for Sandy/Ivy Bridge (0 first context of the first core, 1 first context of the second core ...) processors, which is different from the one used on PHI (0 first context of the first core, 1 second context of the first core ...).
  * always use the compile flag <code> -O3</code> to compile FastFlow code
  * use the FastFlow version in <code>/home/spm1501/fastflow</code> that is use the compile time flag <code>-I /home/spm1501/fastflow</code>

=== MIC0 and MIC1 === 
You can use both the accelerators available on the machine (namely MIC0 and MIC1), despite the fact the examples in this page alway use mic0 ... 

=== Additional libraries ===
In case you need additional libraries on the MIC (e.g. libomp6.so) you must copy the library from <code>/opt/intel/compilers_and_libraries/linux/lib/intel64_lin_mic</code> to the MIC (with an SCP command) and then you should tell the MIC run time where to look for the library: 
<code>export LD_LIBRARY_PATH=."</code>



=== Documentation ===
Available documentation on the Xeon PHI and the relative programming tools may be accessed at the [[https://software.intel.com/en-us/mic-developer|Intel Xeon PHI Developer Zone]]



==== More documentation =====

  * [[https://software.intel.com/en-us/articles/intel-and-third-party-tools-and-libraries-available-with-support-for-intelr-xeon-phitm|list of tools]] available for Xeon PHI
  * {{:magistraleinformaticanetworking:spm:knc_scif_userguide.pdf|SCIF}} user guide  
  * [[http://www.prace-ri.eu/best-practice-guide-intel-xeon-phi-html|best practice]] guide for Xeon PHI from PRACE project
  * [[http://goparallel.sourceforge.net/wp-content/uploads/2012/10/SF12_SFTS001_101.pdf|Slides]] on Xeon PHI offloading